SoC Platform Architecture

Jan 2023 - Present
Apple, Cupertino, CA

GPU Power Architect Intern

May 2022 - August 2022
NVIDIA Corporation, Santa Clara (Remote)
  • Analyze performance and power characteristics and modelling for Deep Learning workloads on GPUs.

Digital Design Engineer

July 2018 - August 2021
Texas Instruments India, Bengaluru
  • Performed verification of multiple System-on-Chip peripherals, DMA, memory, and security subsystems
  • Automated design and verification methodologies for consecutive spin devices for TI Wireless Connectivity products leading to an improved speed up of nearly 80 man-hours between each device
  • Supervised and mentored a 2-month intern (Summer 2021); trained and mentored a new college graduate for 1 year (2020-21)
  • Collaborated with the Applications team to provide quick software solutions for multiple client requirements and silicon bug resolutions based on the understanding of underlying hardware architecture
  • Reviewed and fine-tuned specifications working with the architects and verification team for security peripherals, low-power cross-clock/power domain infrastructure, and Boot FW development for the microcontroller-based products

Digital Design Summer Intern

May 2017 - July 2017
Texas Instruments India, Bengaluru

Evaluated solutions for performing analog defect-based test for Power management and Analog-to-Digital Converter modules

Founder Member and Team Lead

March 2015 - May 2018
Integrated Resources and Information Sharing (IRIS), NITK Surathkal
More info...
  • Development of website comprising of various student, administrative and non-administrative modules
  • System and network architecture design with auto deployment using Continuous Integration and Continuous Deployment (CI-CD)
  • Worked with various stakeholders - faculties, university administration, non-technical staff to understand requirements and challenges faced in offline mode of work
  • Mentored a team and worked on developing multiple modules and helping in seamless transition from the offline to the online mode of work

Summer Research Intern

May 2016 - July 2016
Indian Institute of Technology (IIT), Bombay
  • Developed 22 functions for Signal Processing Toolbox as part of Scilab contributing to Free and Open-Source Software for Education (FOSSEE) organization
  • Optimized 9 functions for use in microcontroller-based applications for low-power implementations


I focus on interdisciplinary domains like electronics, data systems, networks and architecture with my work targeting the hardware and software codesign.

  • Studied datacenter tax on network and compression for clustered MongoDB setup on a benchmark suite to find hardware bottlenecks and propose optimization in underlying API usage for better L3 cache hit ratio.
  • Proposed the use of existing solutions to reduce the application to kernel overhead for network operations and showed the benefit of using hardware accelerators where bulk data compression during the logging service can be beneficial
  • Implement a traffic and bandwidth driven Network-on-Chip node placement algorithm on Fluid, a framework for defining Systems on FPGA using Python
  • Bachelor’s Major Project to implement power-optimised re-configurable CNN memory accelerator on FPGA
  • Project aims to optimise power and speed with minimum impact on area for performing CNN operations
  • Reduced heavy memory accesses using simpler yet effective weights and created alternate memory mapped cache path for CNN operations
  • Team - Naadamaya (ID: 24725)
  • Algorithmic beat tracking is a challenge for real-time implementation
  • Developed causal beat tracking algorithm - includes onset detection, Beats Per Minute(BPM) estimation, beat phase estimation and beat prediction
  • A self-motivated project to implement packet switching using GPUs
  • Core networking functions such as lookups, hash calculation or encryption to be executed in parallel for multiple packets
  • GPU implementation provided flexibility over ASIC implementations for new algorithm implementations
  • Optimising CPU-GPU interactions, reduce DRAM access, faster lookups help in Named Data Networking (NDN) applications
August 2015 - March 2017
  • Funded Industrial collaboration project with Daimler India Commercial Vehicles Pvt. Ltd.
  • Design and Development of an Automated Guided Vehicle
  • Worked on the electronic controller board of the vehicle and designed PCB for the same
  • Worked on understanding Human-Computer Interaction of workers and the AGV in an industrial setup to implement better safety hooks in the vehicle
  • Development of a tablet with refreshable tactile interface to realise physical shapes and terrains to help visually challenged
  • Prototype on dynamic 3-D surface formation inspired from MIT’s inFORM
  • Team - 50Hz of India (ID: 24492) - Top 15 finalists worldwide
  • Involved analyzing power signatures from multimedia recordings and classifying them into its respective power grids
  • Electric Network Frequency (ENF), Feature extraction and classification
  • Designed circuit to accurately capture the local electricity source waveform and correlate with audio recordings in same environment

Skills & Proficiency


Hardware design and System Verilog





Ruby on Rails