Digital Design Engineer

July 2018 - August 2021
Texas Instruments India, Bengaluru
  • Performed design and verification of multiple System-on-Chip serial peripherals, DMA, memory (incl. non-volatile memory controller), interconnect and security subsystems
  • Automated verification of consecutive spin devices for TI Wireless Connectivity products leading to an improved speed up of nearly 80 man-hours between each device
  • Managed a 2-month intern; trained and mentored a new college graduate for 1 year
  • Collaborated with Applications team to provide quick software solutions for multiple client requirements

Digital Design Summer Intern

May 2017 - July 2017
Texas Instruments India, Bengaluru

Evaluated solutions for performing analog defect-based test for Power management and Analog-to-Digital Converter modules

Founder Member and Team Lead

March 2015 - May 2018
Integrated Resources and Information Sharing (IRIS), NITK Surathkal
More info...
  • Development of website comprising of various student, administrative and non-administrative modules
  • System and network architecture design with auto deployment using Continuous Integration and Continuous Deployment (CI-CD)
  • Worked with various stakeholders - faculties, university administration, non-technical staff to understand requirements and challenges faced in offline mode of work
  • Mentored a team and worked on developing multiple modules and helping in seamless transition from the offline to the online mode of work

Summer Research Intern

May 2016 - July 2016
Indian Institute of Technology (IIT), Bombay
  • Developed 22 functions for Signal Processing Toolbox as part of Scilab contributing to Free and Open-Source Software for Education (FOSSEE) organization
  • Optimized 9 functions for use in microcontroller-based applications for low-power implementations


I focus on interdisciplinary domains like electronics, mechanical, data systems, networks and architecture with my work targeting the hardware and software areas.

  • Bachelor’s Major Project to implement power-optimised re-configurable CNN memory accelerator on FPGA
  • Project aims to optimise power and speed with minimum impact on area for performing CNN operations
  • Reduced heavy memory accesses using simpler yet effective weights and created alternate memory mapped cache path for CNN operations
  • Team - Naadamaya (ID: 24725)
  • Algorithmic beat tracking is a challenge for real-time implementation
  • Developed causal beat tracking algorithm - includes onset detection, Beats Per Minute(BPM) estimation, beat phase estimation and beat prediction
  • A self-motivated project to implement packet switching using GPUs
  • Core networking functions such as lookups, hash calculation or encryption to be executed in parallel for multiple packets
  • GPU implementation provided flexibility over ASIC implementations for new algorithm implementations
  • Optimising CPU-GPU interactions, reduce DRAM access, faster lookups help in Named Data Networking (NDN) applications
August 2015 - March 2017
  • Funded Industrial collaboration project with Daimler India Commercial Vehicles Pvt. Ltd.
  • Design and Development of an Automated Guided Vehicle
  • Worked on the electronic controller board of the vehicle and designed PCB for the same
  • Worked on understanding Human-Computer Interaction of workers and the AGV in an industrial setup to implement better safety hooks in the vehicle
  • Development of a tablet with refreshable tactile interface to realise physical shapes and terrains to help visually challenged
  • Prototype on dynamic 3-D surface formation inspired from MIT’s inFORM
  • Team - 50Hz of India (ID: 24492) - Top 15 finalists worldwide
  • Involved analyzing power signatures from multimedia recordings and classifying them into its respective power grids
  • Electric Network Frequency (ENF), Feature extraction and classification
  • Designed circuit to accurately capture the local electricity source waveform and correlate with audio recordings in same environment

Skills & Proficiency


Hardware design and System Verilog





Ruby on Rails